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My job description: |
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To forward the project, I'm often
asked to: ·
Design
timing critical parts or blocks with asynchronous interfaces. ·
Design
high-complexity functions, often being the driving person in ·
Setting up synthesis tools and handle various DFT
issues. ·
Hold
small in-house courses. See a list below. ·
Last,
but maybe the most important function, I usually |
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Some courses I've designed and held: |
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Connecting over clock domains |
Setup/hold, metastability, asynchronous and
isochronous inputs, double-clocking, double-buffering, fifos, circular
buffers. A structured approach to inter-clock domain communication. Clock:
gating, dividing and multiplication. Clock handling and limitations in FPGAs
and ASICs. 2 h lecture. |
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Some things simulation and synthesis courses
do not teach. |
Block- and chip-level design flows. Back-end design
flow. Floorplanning and clock tree design. PVT variation space and levels of
simulation accuracy. Deep sub-micron delay calculation. Synthesis scripting
and setup for successful layout. Basics of static timing analyses. 3 x 2 h
lectures. |
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Verilog workshop |
When several design-entry tools are available and
engineer experience vary: the style, look, feel, testability and
error-prone-ness of the code differs a lot even within a design group. In this workshop all participants solve the same problem and then we go through all solutions giving (usually) constructive comments. Very efficient way to improve tool usage and enhance understanding of code style issues. Up to 6 h own work + 2 hour workshop. |
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VHDL workshop |
Same as above but in VHDL. |
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Understanding Synthesis |
Basics of timing analyses, "Cloud
diagrams" to improve design understanding. The different phases within
the synthesis process. Setting up I/O timing. How to write fast code.
Architectural and layout dependant limitations. Synthesis scripting. 2 h
lecture. |
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101 beautiful uses of LFSRs. |
Still under development. |
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