Frequently asked questions about ASICs | |||||
What is an ASIC ? | |||||
Application Specific Integrated Circuit. Ten years back the electronic designers used several standard chips together on a board to create a special function. This is too big, too slow, too easy to copy or too power-consuming for many applications today. The solution is to put the whole design into the same chip, an ASIC. A modern ASIC is big; I have worked with 100 Mgate ASIC's. For comparison: A Z80 processor will need about 0.02 Mgate. An ASIC will typically take five to ten man-years to design. |
|||||
What does it look like ? | |||||
The buttons below show an ASIC I've designed. The finest details of the asic is 0.35 µm (i.e. invisible even on the close-ups). | |||||
Click pictures to see close-ups. |
|||||
The naked chip is about 12 x 12 mm. The lighter areas are memories. | The chip mounted into a package. Note the thin silver wires connecting the chip to the gold pins. | ||||
Where do you find ASIC's ? |
|||||
Almost in all electronic equipment: PC's, Mobile phones, Answer machines, Watches, CD players, Pacemakers, Telecom switches, Synthesizers, Toys etc |
|||||
What is hardware description languages ? | |||||
The traditional way to describe a design is to draw a schematic diagram. Today when a design can consist of up to a 10.000.000 units (gates, registers) this is considered too slow, too hard to overview, too hard to verify etc. Using a hardware description languages (such as VHDL or Verilog) it is possible to describe a behavior of a circuit. This CODE can then be simulated (verified) and synthesized (turned into a schematic diagram). |
|||||
Why do you use workstations/UNIX ? |
|||||
|
|||||
What tools do you use ? |
|||||
For design entry: | Summits VisualHDL, Mentor Graphics Renoir |
||||
For synthesis: | Synopsys Design_compiler, Synopsys Fpga_express, Synplicitys Synplify |
||||
For simulation: | Mentor Graphics Modelsim | ||||
ATPG generation: | Synopsys Test_compiler | ||||
Static Timing Analysis: | Mentor Graphics QuickPath, Quad design Motive. |
||||
+ a zillion smaller tools which usually are vendor-dependant. | |||||
What vendors have you worked with ? |
|||||
Texas Instruments, TGB1000 | 0.7µ, 5V, BiCMOS Gate array | ||||
Motorola, M5C | 0.5µ, 3.3V, CMOS Gate array | ||||
VLSI Technology, VSC883 | 0.35µ, 2.5V, CMOS Standard cell | ||||
Matra MHS, MG2 | 0.5µ, 5V, CMOS, Embedded gate array | ||||
LSI technology, G12-d | 0.18µ, 1.8V, CMOS, Standard cell | ||||
TSMC, 013G | 0.13µ, 1.2V, CMOS, Standard cell | ||||
What is deep sub-micron technology ? |
|||||
The most important parameter for chip design is the size of the smallest details on the chip. 'Deep sub-micron' means much smaller than micro-meter (1 µm = 0.001 mm or 0.00004 inch). Today we are looking towards 0.13µ technologies. Using a smaller technology will get you:
|
|||||
What are the most important factors when developing new products ? |
|||||
- Time to market | The most important factor ! | ||||
- Power consumption | Especially for battery operated equipment. | ||||
- Manufacture cost | E.g. toys. | ||||
- Product size | E.g. mobile phones. | ||||
- Testability | Check that the chip is correctly manufactured. | ||||
- Verify-able | Check that the chip is correctly designed. | ||||
- Reusable design | Engineering cost is often the highest cost. | ||||
Home |